library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ImageDataGen2 is
  Port(PixelClk : out std_logic;
       Data : out std_logic_vector(15 downto 0);
       RowEN : out std_logic);
end ImageDataGen2;

architecture beh of ImageDataGen2 is

signal pclk : std_logic:='0';
signal pdata : std_logic_vector(15 downto 0):=(others=>'0');
signal hsize : natural:=752;
signal vsize : natural:=480;
signal row,frame : std_logic:='0';

signal vblank : natural:=45;
signal hblank : natural:=94;

signal rowCount,colCount : integer:=0;

signal clktime : time:=19 ns;

type states is (FrameStartBlank,FrameEndBlank,Active,HorizBlank,VertBlank);
signal cs : states:=FrameStartBlank;


begin
  
  pclk<= not pclk after clktime;
  PixelClk<=pclk;
  RowEN<=row;
  
  process
  begin
    --setup time
    wait for 1 us;
    
    --Output images
    while(true) loop
      frame<='1';
      --frame start blanking
      cs<=FrameStartBlank;
      for i in 1 to (hblank - 23) loop
        wait until rising_edge(pclk);
      end loop;
      --Image Loop
      for i in 1 to (vsize - vblank) loop
        rowCount<=i;        
          --Row Loop
          for r in 0 to hsize loop
            colCount<=r;
            if r < (hsize - hblank) then
              cs<=Active;
              --Col Loop/Pixel loop
                Data<=pdata;
                row<='1';
                wait until rising_edge(pclk);
                pdata<=pdata + 1;
            else
              cs<=HorizBlank;
              wait until rising_edge(pclk);
              row<='0';
            end if;
          end loop;
      end loop;
      cs<=FrameEndBlank;
      --frame end blanking
      for i in 1 to 23 loop
        wait until rising_edge(pclk);
      end loop;
      frame<='0';
      --Vertical Blanking
      row<='0';
        for i in 1 to vblank loop
          --Row Loop
          for r in 0 to hsize loop
            colCount<=r;
            if r < (hsize - hblank) then
                wait until rising_edge(pclk);
                cs<=VertBlank;
            elsif i < vblank then
              wait until rising_edge(pclk);
              cs<=HorizBlank;
            end if;
          end loop;
        end loop;
    end loop;  
  
    wait;
  end process;
end beh;